What was actually shown
At the OCP Global Summit in San Jose on October 12, 2026, AMD CEO Lisa Su held up a piece of silicon from the sixth-generation EPYC family. It is code-named Verano, and it is the first EPYC processor with an LPDDR memory interface. The modules are SOCAMM2, which is JEDEC standard JESD328, defined for low-power DRAM intended to serve as main memory in data center and AI server systems.
That is the surface version. The part worth reading is why a server platform would adopt a memory standard that has belonged to laptops for a decade. AMD’s positioning for Verano is performance per system watt, not conventional CPU benchmark performance. Earlier reporting put the part at up to 72 cores with a 24-channel LPDDR5X configuration. Reporting from the summit describes a demonstrated part with as many as 192 cores. AMD has not published a full product specification covering the lineup, so the core count is unconfirmed and the difference between the two figures may reflect separate configurations. Production is stated for the first half of 2027.
Two other details from the same keynote carry weight. Verano is described as optimized for the lowest system power with an updated CPU-to-GPU bandwidth, which is what makes it useful as a host node rather than a compute part. It is reportedly designed for xGMI link speeds reaching 112 Gbps, aimed at future Instinct installations including the MI500 generation. A CPU that moves bytes to an accelerator faster than it computes is a memory-platform product wearing a CPU badge.
The module format is the actual engineering decision
LPDDR is soldered to the board in nearly every device that uses it. In a phone that is harmless, because nobody repairs a phone by replacing a memory module. In a rack it is a warranty problem: a failed module means a failed board, and a board in a 133 kW rack is not a cheap unit to swap.
SOCAMM2 is the same electrical standard in a removable package. The memory type is not the news. The socket is. That is the single line that separates this from a power-efficiency talking point, and it is why the module makers lead with serviceability before they lead with watts.
The published numbers, stated as manufacturer claims rather than measured results:
| Item | SOCAMM2 (LPDDR5X) | DDR5 RDIMM |
|---|---|---|
| Standard | JEDEC JESD328 | Registered DIMM, unbuffered ECC server path |
| Operating voltage | 1.05 V | 1.1 V nominal |
| Per-module bandwidth | Up to 153.6 GB/s (Samsung claim, 2.6x conventional DDR server memory) | Not published as a per-module figure |
| Power vs RDIMM | Over 70% better power efficiency (Samsung); over 55% less power at more than twice the bandwidth; up to 61% less active power and up to 80% less system standby power (Micron) | Baseline |
| Capacity per module | Up to 256 GB (Micron 1-gamma process, 32 Gb die); 192 GB tier | Typically 32 to 64 GB |
| Serviceability | Removable module | Removable module |
Read those as vendor claims, not independent measurements. No third party has published a head-to-head test of a Verano board against a conventional EPYC board. What is not in dispute is the direction: two 24-channel loadouts do the same job at the socket, and one of them costs a fraction of the watts.
Why memory power became a line item at all
The supply side explains the urgency. Samsung and SK Hynix together control roughly 64% of global DRAM revenue, and their finished memory inventory fell below 10 days of supply on September 7, 2026. Conventional DRAM contract prices rose 90% to 95% quarter over quarter in the first quarter of 2026. A 36 GB 12-Hi HBM3E stack was tracked at $300.87 on a spot index in mid-September, up 14% year over year.
The mechanism is allocation, not raw wafer capacity. Every wafer redirected to HBM4 is a wafer that is not becoming a DDR5 module for a desktop, a laptop, or a general-purpose server. HBM consumes roughly four times the wafer area of equivalent conventional DRAM, which is why a memory line item in an AI accelerator bill of materials runs from $2,400 to $6,500 per unit.
A low-power module does not add wafers. It changes what the same wafer is worth per watt delivered, which is the only lever a system designer has when memory is already the largest controllable line in the rack. The metric Nvidia put on its DSX AI Factory platform is tokens per watt, and memory sits inside that denominator.
What this looks like on a machine you already own
The consumer version of this memory decision is already shipping, and it is the version most readers can actually buy. The AMD Ryzen AI Max+ 395 reaches its memory through a 256-bit LPDDR5X-8000 interface rated at 256 GB/s. Real sustained throughput on the 128 GB machines lands near 215 GB/s, about 84% of the published figure. That gap is the derate to apply to any unified-memory bandwidth claim.
That memory is soldered. There is no upgrade path on any configuration, and every price point sits at the same 256 GB/s regardless of how many gigabytes are populated. The 2026 memory shortage has pushed 128 GB machines to $3,449 and up.
So the interesting question is what actually sets throughput on a machine you own, and that is measurable. I ran a real request against the llama.cpp endpoint on my own box: a Ryzen 9 5900X, 64 GB DDR4, an RTX 3090 with 936 GB/s of GDDR6X, serving a 125B MoE at IQ2_XS quantization across a GPU, RAM, CPU and SSD split.
A 1,028-token prompt: prefill 1,295 ms, 793.8 tokens per second as the engine reports it. Generation of 300 tokens took 3,409 ms, 88.0 tokens per second engine-reported, 85.6 tokens per second measured end to end from the client. The difference between those two numbers is request handling and tokenization, and it is the number an agent loop actually experiences.
The same prompt sent again hit cache: prefill dropped from 1,295 ms to 39.2 ms. Generation was unchanged. Prefill is a one-time cost per unique prompt. Decode is not.
Short calls are where the overhead shows. Four small requests, 60 output tokens each: median non-inference time of 231 ms per call against a total wall time of 0.806 seconds. That is roughly 28% of a short request spent on nothing that touches the model. An agent making twenty small calls per task pays that twenty times.
The arithmetic ties back to the memory subsystem, which is the whole point. Reverse the measurement: 88 accepted tokens per second against a 936 GB/s bus means about 10.6 GB of data moved per accepted token. I cannot decompose that figure into which tier served each byte without more instrumentation, but the draft counters show why it is high: 195 draft tokens were generated to land 138, so every accepted token costs more than one trip across the memory tiers, and on a split model those trips cross GPU, RAM and storage. The engine is memory-bound, not compute-bound. No amount of arithmetic throughput changes that ceiling, because the part is not doing arithmetic per token. It is moving bytes per token, and the only lever on a device like this is bytes per watt, which is exactly what a low-power module is trying to buy.
SOCAMM2 does not change a desktop board. There is no socket on a Strix Halo machine, and there will not be one. What it changes is the price of bandwidth per watt at the level where the memory bill is decided, and that price eventually shows up in whatever hardware is affordable on a desk.
The decision this actually affects
If you are buying memory today, the form factor question is still open on the consumer side, and it is not a small one. A desktop UDIMM kit is replaceable, upgradeable, and priced against a market that has already moved. A soldered unified-memory machine is a fixed capacity you cannot change after purchase, which means the capacity decision is the purchase decision.
For a build where the memory pool is the constraint, the practical split is this. If the model fits in a discrete card’s memory, buy the card and put a replaceable kit behind it, because the kit is the part you will change in a year. If it does not fit in a card, the machine is defined by its bandwidth, and soldered or socketed does not matter to you at all.
The hardware tiers are worked through in the best hardware for running local LLMs guide, and the memory allocation side of the same shortage is in what a 3x DRAM price means for local LLM builds. The power side, which is where a low-power module actually pays for itself, is in what power capping costs a local LLM build.
What to buy if this is the workload
Three listings, each checked against its actual product page today, prices approximate as of October 15, 2026.
AMD Ryzen AI Halo developer platform, 128 GB unified memory, about $3,999. The listing states 128 GB LPDDR5X at 8000 MT/s with 256 GB/s of bandwidth and support for models up to 200 billion parameters. This is the soldered version of the memory decision, bought at the price of the socket you do not get. It is the right machine when the model is the point and the capacity is decided up front.
MINISFORUM MS-S1 Max, Ryzen AI Max+ 395, 128 GB LPDDR5X, 2 TB SSD, about $3,879. Same memory architecture, different chassis, with two 10 GbE ports and USB4, which matters if the machine is a serving node rather than a workstation. Listing shows low stock at the time of checking.
G.SKILL Flare X5 64 GB kit (2×32 GB), DDR5 6000 CL30, desktop UDIMM, about $1,269. This is the path that still has a socket, and it is the only one of the three you can change later. Form factor checked on the listing: 288-pin UDIMM for desktop boards, not SODIMM. The kit requires BIOS adjustments to reach its rated speed, which is a fair warning to state.
What is not settled
AMD has not published a product specification for the Verano lineup: core counts, clock frequencies, cache sizes and power requirements are unconfirmed. The 192-core figure comes from summit reporting, not a datasheet. The power-efficiency numbers come from module makers, not a third-party test. The platform is a 2027 product.
What is settled is the direction. A memory standard built for phones is being put on a serviceable server board because the watts per byte are the constraint, and the module format is what makes that acceptable in a rack you have to maintain. On a machine you own, the same standard is already there, soldered, with no socket and no upgrade path. That is the part a buyer can act on today.
