What Intel actually announced
At the Open Compute Project Global Summit on October 12, Intel gave its Crescent Island accelerator a product name — the Intel GPU D-Series — and disclosed its specifications for the first time. The numbers: 1.3 petaflops of FP8 compute, 1.5 TB/s of memory bandwidth, up to 480 GB of LPDDR5X, all inside a 350-watt envelope, on a standard PCIe card that is air-cooled. Intel’s own branded card carries 160 GB; the design allows partner-built ODM cards up to 480 GB. A single card is claimed to serve models up to 300 billion parameters, and an eight-GPU system more than a trillion.
There is no launch date and no price. Customer sampling is underway. That is the whole announcement, and it is enough, because the interesting part is not the compute figure. It is the memory type. The D-Series is the first mainstream data-center inference accelerator that does not use HBM.
Why the memory type is the story
Every serious inference accelerator from NVIDIA and AMD puts stacked memory in the package. That is what creates the bandwidth: an HBM3E stack exposes 1,024 data pins and delivers roughly 819 GB/s to 1.2 TB/s per stack, and HBM4 doubles the interface to 2,048 bits for up to 2 TB/s per stack. The cost is packaging and wafer area, and those are the two things currently being rationed.
The pricing follows the allocation. HBM4 contract pricing moved roughly 117% week-on-week in early October, per the market trackers. Seoul Economic Daily puts a 12-high 36 GB HBM4 stack at about $1,300 next year against roughly $600 this year. Micron said on its FQ4 call that more than 75% of FY2027 shipment volume is already committed at prices well above 2026 levels, and that HBM will consume 30% of DRAM fab capacity by 2027 against 20% now. Counterpoint reports that most HBM4 in NVIDIA’s Rubin platform keeps the 12-high stack configuration, which keeps the capacity squeeze on ordinary DRAM in place. This is the mechanism behind DRAM prices tripling on a home build: not a shortage of DRAM cells, but a shortage of the packaging and fab allocation that turns DRAM cells into accelerator memory.
LPDDR5X sits outside that queue. It is planar DRAM, soldered near the processor, running a narrow interface fast. It has no RDIMM variants, caps at roughly 64 GB per package, and delivers on the order of 68 GB/s per package. It is cheap because nobody is fighting over it. Intel’s bet is that if you build a very wide LPDDR interface instead of a stacked one, you can buy bandwidth at commodity DRAM prices instead of at HBM prices.
1.5 TB/s from LPDDR5X is not a modest claim. It requires something like 22 independent 64-bit channels at 8,533 MT/s on one board. For comparison, NVIDIA’s Grace CPU carries up to 480 GB of LPDDR5X at up to 512 GB/s, in roughly 16 watts. Intel is quoting three times that bandwidth at the same capacity. The capacity figure is not new; the interface is.
What 1.5 TB/s actually buys you
Decode throughput is a bandwidth problem before it is a compute problem. Each generated token streams the model’s weights once. So the ceiling is bandwidth divided by the bytes touched per token.
Take a 300-billion-parameter dense model at 4-bit weights: about 150 GB streamed per token. At 1.5 TB/s theoretical, that is a ceiling of 10 tokens per second, and real hardware runs at roughly half of theoretical peak once refresh cycles, ECC and command overhead are counted. So the practical figure is single digits. A card that holds a 300B model and produces 5 tokens per second is a card that holds a 300B model and produces 5 tokens per second. Capacity decides whether a model fits. Bandwidth decides whether it is usable.
The exception is mixture-of-experts models, where the bytes touched per token are only the active subset. This is where the D-Series argument becomes coherent, and it is measurable on a small machine.
A measurement on my own hardware
I run on a 125B MoE served by Strata over a Ryzen 9 5900X, 64 GB of DDR4 and an RTX 3090 — 936 GB/s of GDDR6X, a memory subsystem that costs almost nothing per gigabyte. I fed it a real prompt: the text of Intel’s own OCP press release, 493 tokens, not a one-line greeting.
Engine-reported numbers for that request: 514 tokens/s prefill, 93.8 tokens/s decode. Wall-clock decode measured from the client: 55.3 tokens/s. The engine counts its own generation loop; the client counts the whole request. The gap is request handling, tokenization and network — and that gap is the number an agent loop actually experiences.
The arithmetic behind 93.8 tokens/s on 936 GB/s is about 10 GB of weights touched per token. That is what a MoE routing a small active subset looks like. A dense 125B model at the same quantization would stream 70-plus gigabytes per token and run at a fraction of that speed on the same card. The card is not fast. The model is sparse.
Speculative decoding is the other half. That request generated 115 draft tokens and accepted 88 — 76.5% acceptance. Accepted draft tokens count as produced output, so the engine’s decode figure includes them. Speculative decoding is a bandwidth trick as much as a compute trick: it amortizes one weight-streaming pass across several tokens. On a short completion, the same engine reported 138 tokens/s against 97.7 tokens/s wall-clock.
Per-request overhead matters more in an agent loop than in a single long generation. On the short request, 0.05 seconds of a 0.31-second request was not inference. On the long one, 0.23 seconds of 2.90 seconds. Roughly 16% of the time, on short calls, is spent doing everything except generating tokens. Intel’s framing at the summit — matching workloads to compute, and its Hot Chips positioning around tokens per watt — is the same accounting, just at rack scale.
The comparison that decides a purchase
Prices below are what I checked today, approximate, and they are the only prices in this article that are quotable. Intel has not published a price for the D-Series, so that row has no dollar figure — it has specs.
| Memory subsystem | Theoretical bandwidth | Capacity ceiling | What it costs |
|---|---|---|---|
| LPDDR5X, per package | ~68 GB/s | ~64 GB per package | Commodity DRAM pricing, no packaging premium |
| Intel GPU D-Series | 1.5 TB/s | 160 GB Intel card, up to 480 GB ODM | Not announced |
| AMD Strix Halo (Ryzen AI Max+ 395) | 256 GB/s theoretical, ~215 GB/s measured | 128 GB, soldered, not upgradable | $3,499 to $3,879 as listed today |
| HBM3E stack | 819 GB/s to 1.2 TB/s per stack | 36 GB (12-high) | ~$600 per stack this year |
| HBM4 stack | ~2 TB/s per stack | 48 GB (16-high schedules) | ~$1,300 per stack projected next year |
| RTX 3090, GDDR6X | 936 GB/s | 24 GB | Planar DRAM on a board, no interposer |
Read the table as a ratio, not as a ranking. The D-Series holds three times what an H200 holds at about a third of its bandwidth. That trade is only good if the model you serve is sparse. It is a bad trade for a dense model, and a good trade for a MoE with a small active footprint — which is exactly the class of model Intel names as its target, and exactly the class that runs acceptably on hardware that costs almost nothing per gigabyte.
What this means for a home build
Nothing ships for a home build here. The D-Series is a data-center card with no price, and the tier structure in best hardware for running local LLMs in 2026 is unchanged by an announcement that has no pricing attached to it.
What changes is the argument. If a hyperscaler can serve a 300B model on planar DRAM at 1.5 TB/s, the API pricing for that class of model is no longer anchored to HBM scarcity. That is the second-order effect, and it lands on anyone paying per token.
For the machine on your desk, the same logic already applies in miniature. The reason a 125B MoE runs at 90-plus tokens per second on a card with 936 GB/s is that the model is sparse and the memory is cheap. The reason a 128 GB Strix Halo box runs a dense 70B model at around 6 tokens per second is that its 256 GB/s bus is the whole story, regardless of how much capacity it holds. Capacity is not speed. If you are choosing between a wide cheap bus and a narrow fast one, you are choosing between fitting a model and answering quickly.
What you would actually buy for this workload
If the goal is a large model resident in memory without an offload trip per token, the current LPDDR tier is the honest expression of Intel’s argument at consumer prices. The GMKtec EVO-X2 is listed today at about $3,500 for a Ryzen AI Max+ 395 with 128 GB of LPDDR5X, and the MINISFORUM MS-S1 MAX at about $3,879 for the same memory with a PCIe x16 slot and dual 10GbE. Both are soldered, so capacity is a purchase decision, not an upgrade path. Both are bandwidth-limited at 256 GB/s. You are buying a wide bus, not a fast one.
If the goal is planar DRAM at commodity prices, a Crucial Pro 64 GB DDR5 kit — 2×32 GB, 6000 MHz, desktop UDIMM — is listed at about $950 today. That is roughly $15 per gigabyte for memory that no packaging queue is fighting over, against $1,300 for a 48 GB HBM4 stack next year. The difference is not the cells. It is the interposer.
And the storage tier is part of the inference path when a lookup table is read per token. A WD_BLACK SN850X 2 TB with heatsink is listed at about $400; the listing is now flagged as superseded by Sandisk’s Optimus GX PRO 850X, which is worth knowing before you buy it.
What this announcement does not do
It does not ship. It has no price, no launch date, and no independent reproduction of the 1.3 petaflop figure — those are Intel’s own targets, stated at a summit, and they remain the project’s own until someone else measures them. The manufacturing node is undisclosed. The 480 GB configuration is an ODM option, not a card you can order.
What it does establish is that the memory interface is now a strategic choice rather than a default. Microsoft went the other way on the same day: Maia 300 takes eight HBM4 stacks, up from six HBM3E stacks in Maia 200, with 2.5 times the HBM bandwidth and roughly 40% more output per megawatt. Two companies, same week, opposite bets. One is paying the packaging premium. The other is trying to route around it. The one that wins depends on whether the models being served are dense or sparse — and that is a question you can answer for your own workload before you buy anything.
