The 273 GB/s Bus: What Axera Says About the Ceiling on Local Decode

What was actually announced

On 13 October, at the Shanghai industrial expo, Axera showed the AX8860: a 6 nm part with sixteen Arm Cortex-A55 cores, an NPU rated at 256 TOPS of dense FP4, and a memory controller that can hold up to 128 GB of LPDDR5X on a 256-bit bus at 273 GB/s. The same day Sipeed opened reservations for the MaixStation, a 363 cm³ box built around that chip, and said it beats NVIDIA’s DGX Spark on Qwen 27B: 25% faster prefill, 30% faster decode, at 40 W, for about half the price.

The memory row is the part worth reading. The GB10 inside every DGX Spark runs 128 GB of LPDDR5X on a 256-bit bus at 273 GB/s. Axera chose the same bus width, the same speed, the same bandwidth, to the digit. AMD’s Ryzen AI Halo reaches the same 273 GB/s on 192 GB. Three vendors, one number, because that number is the ceiling on the operation that decides single-user speed: a dense model reads every weight once per token.

Prices as stated by the vendor: “$1,xxx” for a 32 GB node, “$3,xxx” for the 128 GB node, which Sipeed told Tom’s Hardware it expects to land near 3,999 dollars. A 128 GB DGX Spark lists at 6,950. Reservations cost 30 dollars, credited as 100 at purchase. Kickstarter at the end of 2026, shipping within three months after it closes.

The physics check, and why the low end is the honest number

Sipeed’s comparison lives on its product page as animated bars, with speculative decoding off on both sides and a note that the chip is “still being tuned.” The values behind the animation, for Qwen3.8-27B dense in FP4:

Take the decode row and divide. A 16 GB FP4 build of a 27B model on a 273 GB/s bus has a ceiling of about 17 tokens per second, and that ceiling assumes the bus runs at 100%: no DRAM refresh, no KV cache reads, no page misses, no attention. The DGX Spark measures 11.5 to 13, which is two thirds to three quarters of its own bus. Sipeed’s low end of 15 is 88% of the bus, which good kernels reach. Its high end of 17 is 99.6%, which nothing shipping reaches during decode.

So the headline numbers are the top of a range that sits on a physical limit, and the defensible claim is the bottom: 8 to 15% faster on a dense model, a tie on MoE decode. Sipeed’s own email to Tom’s Hardware said about 10% ahead on both, which is the low end. The 25% and 30% are the high end. That is the whole story of the announcement, and it is a story about a bus, not about a chip.

What I measured on my own box

I run a machine with the same job and a completely different memory path: a Ryzen 9 5900X, an RTX 3090 with 24 GB of GDDR6X, 64 GB of DDR4 as two 32 GB modules at 2667 MT/s, and an NVMe drive. The engine serves a 125B MoE with 24,576 experts in 12 GB of VRAM, splitting the rest across system RAM, CPU and SSD. Two identical requests against the local API, 8,102 prompt tokens, 200 output tokens, temperature 0:

Prefill reproduced within half a percent. Decode did not: 103.2 against 83.5, a 19% swing between two identical requests. That is normal for speculative decoding, and it is why a single run is a measurement and not a spec. The gap between engine-reported and wall-clock is 4.7% and 4.2% — request handling, tokenization, network. On a local network that gap is small. It is the number an agent loop actually experiences, and it is separate from the number the server counts for its own generation loop.

The memory itself. A 2667 MT/s DDR4 channel is 42.67 GB/s theoretical across two channels. A copy pass on that box — memmove over a 512 MB buffer, ten iterations — measured 16.53 GB/s, which is 38.7% of the channel counted as data moved, or 77.5% counted as memory traffic. A copy touches memory twice, so both numbers are the same measurement read two ways, and only the first is usable bandwidth for an inference loop.

Now put the two numbers side by side. A dense 27B FP4 build is about 13.5 GB of weights, which is the floor; Sipeed’s own chart assumes 16 GB once overhead is included. On the measured 16.53 GB/s, 13.5 GB is a ceiling of 1.2 tokens per second. On Sipeed’s 273 GB/s, it is 20. And my box reports 103.2. The reason is not that my bus is fast. A MoE does not read every weight per token. 103.2 tokens per second against a 1.2 tokens per second dense-model ceiling on the same box means the engine reads a small fraction of the model per token, and the slice it does read sits on GDDR6X, whose 936 GB/s theoretical figure is about 56 times the 16.53 GB/s I actually measured on the DDR4 channel. The engine is a memory-architecture story before it is a compute story.

Bandwidth per dollar, which is the number that decides the purchase

273 GB/s for 3,999 dollars is 0.068 GB/s per dollar. A 64 GB DDR4 kit is a 42.67 GB/s theoretical channel, and the price trackers as of today put 64 GB DDR4 kits from 128 dollars with a median of 140 — 0.30 GB/s per dollar, about four times better. Counted against what I actually measured instead of the theoretical channel, 16.53 GB/s against a 140-dollar kit is 0.118 GB/s per dollar, still 1.7 times better.

That comparison is not an argument for buying RAM. It is the reason the LPDDR price is defensible. The DDR4 channel is shared with the CPU, cannot be driven at its theoretical peak by an inference loop, and cannot be attached to an accelerator without crossing a PCIe hop. A soldered LPDDR5X package on a dedicated 256-bit bus is not being sold as memory. It is being sold as a bus that nothing else competes for. The 3,999 dollars is the bus and the NPU; the 128 GB is nearly free inside it.

The pricing context matters here. DDR4 sits at 8.35 dollars per gigabyte on the October index, up 7.6% in ninety days, and a 64 GB DDR4-3200 kit went from 399 to 490 dollars since late August. The best live value on the tracker is a 64 GB kit at 2.34 dollars per gigabyte, which is what makes a 40 W module reading memory at 273 GB/s competitive with a socketed channel whose price is climbing for reasons that have nothing to do with inference. That is the market signal in the announcement, and it is stronger than the benchmark bars.

What this engine is not

It is not a shipping product. The chip was shown on a stage and is not listed on Axera’s own product pages. Radxa’s preview of the same silicon says up to 128 TOPS; Sipeed and Axera say 256. Nobody has said whether those are two bins of one part or one part described twice.

The measurements are Sipeed’s, on hardware its own page calls unfinished, with no methodology, no prompt lengths, no context sizes, and the top of every range sitting at a physical limit. The four-chip scaling figure is labelled on Axera’s own slide as laboratory simulation data. The frameworks listed — vLLM, SGLang, PyTorch, llama.cpp, Ollama — are written for GPUs; on a custom NPU behind sixteen efficiency cores they provide an API surface while the vendor’s own backend does the work. Whether prefix caching, speculative decoding and concurrent requests survive that is the question that decides whether the bars on the page are the product.

My numbers are one box, one operator, no independent reproduction. The 76.9% acceptance rate is a single request, not a distribution. Treat both tables as measurements from a specific machine, not as specifications.

What to buy if you are not waiting for a Kickstarter

The shape that wins today is a card with its own memory and a bus nobody else contends for. On this box that is the EVGA RTX 3090 with 24 GB of GDDR6X, tracked near 1,850 dollars as of yesterday, which is the cheapest way to get a dedicated high-bandwidth bus on a desktop board. The system RAM behind it is a 64 GB DDR4 kit — desktop UDIMM, not laptop SODIMM — which is the tier the price trackers currently value at 2.34 dollars per gigabyte, and it is doing the offload work the MoE needs. The storage tier is part of the inference path when a lookup table is read per token, so the 2 TB NVMe is not a convenience item here; it is the last level of the memory hierarchy, listed around 180 dollars.

For a build that has to run a dense model rather than a sparse one, the bus is the whole decision, and the hardware ladder is written around exactly that. The trade-off to keep in mind is not speed ranking: more VRAM means fewer offload trips per token, which can offset a slower memory subsystem, and a wide soldered bus buys you the trips you cannot avoid. The same reasoning in dollar form is in bandwidth per dollar, and the price pressure behind it is in what a 3x DRAM price means for local LLM builds. The engine that produced the numbers above is the 125B MoE on a 5900X and a 3090, measured the same way.

If a MaixStation turns up, the test Sipeed invites is the right one: the same model, the same prompts, speculative decoding off, beside a GB10, then on. Until someone else reproduces the bars, they are bars.